What is TSMC 3DFabric? The Chip Stacking Revolution Integrating CoWoS, InFO, and Backside Power Delivery
- Amiee
- 9 hours ago
- 6 min read
What is TSMC 3DFabric? From CoWoS and InFO to BSP, here’s how chip stacking is shaping the future of AI and HPC. Find out why thinner, faster, smarter devices owe everything to packaging.
Chips Aren’t Tofu—But Now You Can Stack Them Like Blocks
Remember stacking Lego bricks as a kid? TSMC (Taiwan Semiconductor Manufacturing Company) is now stacking chips in a similar way. But this is no child’s play—it’s a multibillion-dollar revolution in high-performance computing. TSMC’s 3DFabric technology is quietly rewriting the roadmap for AI chips and HPC (High Performance Computing).
In the era when Moore’s Law is running out of steam, chip designers are searching for new ways to break performance bottlenecks. TSMC’s 3DFabric changes the game by allowing chips to scale vertically like skyscrapers, pushing computational power to unprecedented levels.
So, what exactly is TSMC 3DFabric? Why are giants like NVIDIA and Apple adopting it? What makes this technology so powerful? This article peels back the layers of this cutting-edge packaging solution to reveal how it’s changing the semiconductor industry—one stacked chip at a time.
What is TSMC 3DFabric? An Integrated Platform With Three Core Technologies
TSMC 3DFabric is a comprehensive advanced packaging platform designed to integrate diverse chip functionalities—such as CPUs, GPUs, and memory—into high-density configurations. It comprises three key technologies:
CoWoS (Chip-on-Wafer-on-Substrate): Allows multiple dies to be packaged on a single wafer and interconnected using a silicon interposer, enabling high-bandwidth memory (HBM) and multi-core cooperation. Ideal for large AI models and cloud servers.
InFO (Integrated Fan-Out): A substrate-less packaging solution that extends I/O around the chip, enabling high-density routing and ultra-thin profiles. Best suited for mobile and portable devices—Apple’s A-series processors use InFO.
BSP (Backside Power Delivery): Routes power through the backside of the chip to avoid contention with signal paths. This reduces IR drop and power consumption, improving performance and thermal efficiency. It’s a critical innovation for nodes below 2nm.
This image illustrates a cross-sectional view of an advanced logic chip using backside power delivery technology.
Front Side: Responsible for signal and clock distribution, located in the upper metal layers of the chip.
Back Side: Power and global clock are delivered from the bottom of the chip through a dedicated power layer, helping to reduce IR drop and enhance power integrity.This separation of signal and power paths improves routing efficiency and minimizes noise interference, forming a key part of TSMC’s A16 Super Power Rail (SPR) architecture.
These three technologies form a comprehensive ecosystem: CoWoS provides high-bandwidth interconnects, InFO supports ultra-thin form factors and dense I/O expansion, and BSP redefines power delivery by moving it to the chip’s backside. Together, they enable custom modular heterogeneous integration and are foundational to AI and HPC applications.
From Horizontal to Vertical: Why Stack Chips?
The Limits of 2D Scaling: Moore’s Law is Stalling
Since the 1970s, Moore’s Law has predicted that the number of transistors on a chip would double every 18 to 24 months, driving performance gains. However, as we approach the physical limits of silicon—quantum tunneling, leakage currents, and heat—traditional node shrinking becomes harder and costlier, especially below 5nm.
Emerging demands from generative AI, 5G, AR/VR, and autonomous vehicles require massive compute density and data throughput. This is where 3D ICs (Three-Dimensional Integrated Circuits) come into play. These architectures stack functional dies vertically—such as logic and memory—and interconnect them via TSVs (Through-Silicon Vias) or interposers. This shortens data paths and increases packaging density, continuing Moore’s Law in a “More-than-Moore” direction.
Benefits of Vertical Integration:
Shorter signal paths, lower latency and power: Traditional 2D chips may require signals to traverse across the die or multiple packaging layers. 3D packaging shortens interconnects to microns, enabling near-instantaneous access—like having cache-level proximity—reducing power and latency.
High-bandwidth HBM integration: HBM (High Bandwidth Memory) is a vertically stacked DRAM architecture interconnected via TSVs. Compared to GDDR or DDR memory, HBM offers higher bandwidth and lower power. With CoWoS, HBM stacks can be co-packaged with logic dies, ideal for AI workloads like GPT models, visual inference, and data center processing.
Layered power and thermal design: As more dies are stacked, heat density increases, creating hotspots. Advanced packaging introduces layered heat dissipation solutions—thermal diffusion layers, metal microchannels, and microfluidics. BSP complements this by moving power delivery to the backside, freeing up front-side metal layers and enhancing power integrity. This layered strategy is vital for scaling to 2nm and beyond.
Put simply, 3D packaging is like turning a traffic-clogged 2D highway into a multi-level interchange. Each chip layer handles different data flows or functions, connected by high-speed TSVs, enabling smooth, efficient vertical integration.
TSMC and industry reports confirm that chips using 3DFabric significantly outperform traditional 2D designs in system-level throughput and performance per watt—proof that this packaging revolution is real.
Technical Overview: Application Scenarios for CoWoS, InFO, and BSP
Technology | Full Name | Key Features | Ideal Use Cases | Industry Examples |
CoWoS | Chip-on-Wafer-on-Substrate | Large interposers, HBM support, high bandwidth | AI chips, HPC, GPUs | NVIDIA, Broadcom |
InFO | Integrated Fan-Out | Substrate-less, thin, high I/O density | Mobile SoCs, smartphones | Apple, MediaTek |
BSP | Backside Power Delivery | Power from backside, reduced IR drop | 3D ICs, advanced logic at 2nm | TSMC N2, Intel 20A |
These technologies serve as a modular toolbox, allowing engineers to combine them based on functionality, power, size, and bandwidth needs. For instance, a high-performance AI accelerator might use CoWoS with HBM; a mobile SoC could leverage InFO for its thin profile; and BSP enables stable power for ultra-dense logic designs below 2nm. TSMC’s 3DFabric platform supports a wide spectrum—from data center to edge computing.
Why Industry Leaders Are Embracing TSMC 3DFabric
As AI models like ChatGPT, Llama, and Midjourney grow in scale, they consume hundreds of terabytes per second. Meeting this demand requires unprecedented bandwidth and low latency—where TSMC 3DFabric shines.
Key Advantages:
HBM integration: CoWoS enables tight integration of CPUs/GPUs and HBM stacks. Each HBM layer, connected via interposer, can deliver over 1TB/s of bandwidth. According to NVIDIA, the H100 SXM5 GPU achieves up to 3TB/s, 2x its predecessor.
Heterogeneous integration: InFO and CoWoS support combining different process nodes (e.g., logic with analog) and functional modules (e.g., sensors, memory). Apple’s A-series integrates SoC cores and modules via InFO; NVIDIA’s H100 co-packages logic and HBM with CoWoS, showcasing flexibility and performance.
Power delivery innovation: BSP offloads the power network to the chip’s backside, freeing routing layers for signals and improving power integrity. It also helps with thermal management and power domain partitioning—vital for 2nm and chiplet-era scalability. TSMC and industry roadmaps confirm BSP is becoming a foundational element for future chip architectures.
TSMC is also expanding CoWoS capacity in Southern and Hsinchu Taiwan, while rolling out InFO-L (InFO on Substrate). InFO-L combines RDL density with substrate-level mechanical strength and has been validated by major global customers. It’s well-suited for large SoCs, networking chips, and server-grade applications.
Innovation Amidst Challenge
Every technology leap brings new hurdles. For 3DFabric to scale economically, several issues must be addressed:
Thermal challenges: 3D stack hotspots require new materials and cooling solutions like microfluidics.
Testing complexity: Multi-die packages demand updated EDA tools to catch faults across integration boundaries.
Yield and cost risks: A defect in one die can waste the whole package—heterogeneous yield management is critical.
TSMC is working with EDA vendors (e.g., Synopsys, Cadence) to develop tools for 3D packaging co-design and DFT (Design for Test). Supply chain partners are also upgrading reliability and materials to support these dense, mission-critical packages.
Conclusion: Packaging is the New Frontier
Advanced packaging is no longer just post-fabrication—it’s now central to chip design strategy. From horizontal layouts to vertical stacking, from monolithic SoCs to heterogeneous systems, TSMC 3DFabric is more than an extension of Moore’s Law—it’s a gateway to the era of supercomputing.
For engineers, it’s a design sandbox; for industry, it’s a path to performance and cost efficiency; for the future, it’s how AI, quantum computing, and the metaverse become reality.
That smartphone in your hand or the AI you’re using right now? Chances are, they’re powered by this quiet revolution in packaging.